As the use of semiconductor devices incorporating regulator and DC/DC converter circuits becomes more widespread, it is increasingly important to meet the demands for higher output currents of these devices among others.
In one approach to achieve the high output currents, LDMOS transistors have been attracting much attention, which operate with low on resistance. In addition, the LDMOS transistors are known to have a structure suitable for miniaturization with a decreased chip area yet attaining high withstand voltages.
The “LDMOS (lateral double-diffusion MOS) transistor” is a field effect transistor, including at least a low concentration impurity doped layer (channel well region) formed to surround a source, and for the surface portions of the channel well region under a gate electrode to serve as a channel. In addition, by “conventional MOS transistor” is meant herein one having a drain with an impurity concentration larger than that of a channel region.
FIG. 8A is a diagrammatic cross-sectional view illustrating an N-type LDMOS transistor previously known.
Referring to FIG. 8A, the LDMOS transistor comprises an N-type high resistance silicon substrate 102 and the structure including a polysilicon gate electrode 106 formed with a contiguously underlying gate oxide layer 104, and a channel well region 108 formed by implanting, using the source side edge portion of the gate electrode 106 as a mask, then thermally diffusing P-type impurity ions so as for a portion thereof to serve as a channel.
In addition, N-type low resistance source and drain 110 and 112, respectively, are formed by implanting, using the gate electrode 106 as a mask, and then thermally diffusing P-type impurity ions. Also included are an interlayer dielectric layer 114, and electrode wirings, 116 and 118, connected to the N-type source and drain, 110 and 112, respectively (Japanese Laid-Open Patent Application No. 7-302903).
When an LDMOS transistor is utilized as a high voltage CMOS transistor, several improvements are made to relax the electric field strength in the region between drain and gate electrode. As an example, the thickness at the drain side edge of a gate oxide 104a is increased, as illustrated in FIG. 8B, or alternatively, a field oxide layer 104b is formed in the vicinity of the drain edge portion contiguously under the gate oxide 106, having a thickness larger than that of the gate oxide layer, as illustrated in FIG. 8C.
In addition, the drain 120 in the above structures is formed as a medium concentration drain region contiguously under the thick oxide layer, 104a or 104b, having a concentration of N-type impurity higher than that of the silicon substrate 102, and lower than that of the N-type drain 112. Also, the region 108a in these structures serves as a contact region to be connected to the channel well region 108.
In these structures, however, there arise several drawbacks which will be described as follows. For example, the size of the transistor has to be increased in proportion to the area required for forming the thick oxide layer, 104a or 104b. In addition, the drain resistance is also increased in a similar manner. As a result, the on resistance of the transistor increases.
Also, in the structure of FIG. 8B, another difficulty may arise during photolithography and etching process steps for forming the gate oxide 104a. Namely, transistor characteristics may vary considerably depending on the degree of precision in these alignment and etching steps.
Although the precision in forming the field oxide layer 104b in the drain edge portion shown in FIG. 8C can be increased by using the LOCOS (local oxidation of silicon) method, the transistor characteristics may be deteriorated by the crystal structural disorder which is induced by the field oxide layer formed as above at the region under the gate oxide. In these structures of FIGS. 8B and 8C, therefore, difficulties arise in implementing the miniaturization of the transistors.
In contrast, in the structure without increasing the gate oxide layer thickness in the drain edge portion as shown in FIG. 8A, the concentration of the electric field in this portion may cause the deterioration in threshold voltage by the N-type drain 112 at the region contiguously formed under the gate oxide 104.
Although this deterioration in the withstand voltage can be reduced to a certain degree by lowering the N-type impurity concentration in the oxide side portion of the drain 112, this lowered concentration region, in turn, may cause deteriorating effect on the withstand voltage, since a depletion layer extends to the low concentration region with relative ease even at relatively low voltages applied to the drain 112.
In order to improve the characteristics of the LDMOS transistor by increasing the withstand voltage, there disclosed is a structure including a high concentration drain formed spatially separated from a gate electrode. The structure is illustrated in FIG. 9 as a diagrammatic cross-sectional view of an N-channel type LDMOS transistor previously known (which is hereinafter referred to as ‘Prior art 1’).
Referring to FIG. 9, an N-type drain well region 21 is formed in a P-type semiconductor substrate 1. In the N-type drain well region 21, a P-type well region 23 is subsequently formed. An N-type source 11s is formed in the P-type well region 23.
Also formed in the N-type well region 21 is a medium concentration N-type drain 11d, which is situated spatially separated from the P-type well region 23 having a concentration of N-type impurities introduced higher than that of the N-type well region 21.
Furthermore, an N-type gate electrode 11g, made of polysilicon, is formed with an underlying gate oxide layer 11ox interposed between the gate electrode 11g and the well region 21. This gate electrode 11g is formed in intermediate between N-type source 11s and N-type drain 11d above N-type well region 21, overlying the P-type well region 23, and being separated from the N-type drain 11d. Therefore, the surface of the P-type channel well region 23 under the N-type gate electrode 11g serves as a channel region.
The on resistance of LDMOS transistor is determined by the sum of channel resistance, drain resistance, and source resistance. In the aforementioned N-channel type LDMOS transistor (Prior art 1), its source resistance is decreased by forming the N-type source 11s in the self-aligned manner with respect to the N-type gate electrode 11g. 
However, the drain resistance for drain 21a is relatively high due to a large resistance component of the N-type well region 21, and the drain resistance becomes dominant compared with a decreasing channel resistance in the range of high gate voltage. As a result, there arises a difficulty in the previous channel type LDMOS transistor, in that drain current cannot be increased as desired with the increase in the gate voltage, as illustrated in FIG. 11. Namely, although the drain current Id increases with increasing drain voltage Vg up to approximately 3V, almost no increase in Id is observed beyond this voltage.
In addition, there encountered is another difficulty as illustrated in FIG. 12A, in which a drain breakdown is caused with relative ease after parasitic bipolar operations in the high voltage range for MOS transistor drain.
In order to obviate such difficulties, an LDMOS transistor is disclosed in Japanese Laid-Open Patent Application No. 7-302903, in which its source and drain are formed by double diffusion to thereby improve the transistor characteristics.
Although the electric field strength in vicinity of the drain is relaxed to a certain degree in this stricture through the double diffusion, an overlap exists between the high concentration drain and the edge portion of the gate electrode.
When the present inventors fabricated an LDMOS transistor according to that disclosure, it was found that the drain withstand voltage was obtained approximately 10 V at most, possibly due to a relatively small width of the aforementioned low concentration diffusion region formed by the double diffusion and a concomitant gate modulation effect.
A further assumption was made also by the present inventors from the above results that it was appropriate for a high concentration drain to be formed spatially separated sufficiently from the gate electrode with a distance of 1.0 μm or greater, for example. This and related points will be detailed later on.
In order to improve the drain voltage characteristics, another structure of the LDMOS transistor is disclosed in Japanese Laid-Open Patent Application No. 10-335663, in which implantation and subsequent diffusion process steps are carried out into the surface of a well region between a gate electrode and a high concentration drain in the self-aligned manner for forming a low resistance region.
In this structure, however, a source of the transistor is not formed in the self-aligned manner, thereby resulting in remaining source resistance. As a result, there remains some source resistance, which is insufficient for reducing the on resistance of the transistor.
The present inventor then formed another LDMOS transistor according to the disclosure, with the exception that both source and drain were formed in the self-aligned manner (FIG. 10).
FIG. 10 is a diagrammatic cross-sectional view of the thus formed N-channel type LDMOS transistor (which is hereinafter referred to as ‘Prior art 2’), in which components operating in a similar manner to those of FIG. 9 are shown with identical numerical representation and descriptions thereof are herein abbreviated.
Referring to FIG. 10, there formed are N-type source, drain, gate oxide layer, gate electrode and drain well region, 11s, 11d, 11ox, 11g and 21, respectively, and a P-type channel well region 23. The N-type source 11s is formed in the self-aligned manner with respect to the N-type gate electrode 11g. 
An N-type medium concentration drain region 24 is formed in the surface region of the N-type drain well region 21 on the side of the N-type drain 11d. The N-type medium concentration drain region 24 is formed also in the self-aligned manner with respect to the N-type gate electrode 11g. In addition, the N-type medium concentration drain region 24 is formed with a depth from the surface smaller than that of the N-type drain 11d. 
In the thus formed structure provided with the N-type medium concentration drain region 24, drain currents Id during MOS operations have been improved in the range of high gate voltage Vg over those obtained with the structure of the aforementioned Prior art 1, as shown in FIG. 11.
However, the drain thermal breakdown takes place during parasitic bipolar operations at a drain current Id of approximately 12 mA in the higher range of the applied gate voltage Vg, as shown in FIG. 12B. This is therefore indicative of a still persisting difficulty of low withstand voltage which is unsatisfactory in practice for the LDMOS transistor.
The improvements in transistor characteristics such as withstand voltage and on resistance have been described herein above with respect to the LDMOS transistors, in that its on resistance is reduced and transistor characteristics are stabilized for the LDMOS transistor. It is desirable, however, for the LDMOS transistor to have additional improvements in the reduced on resistance for use in practical device applications as well.
As an example, the gate oxide layer 104 is formed relatively thin so as to reduce the on resistance, and this small thickness has an effect on the voltage applied thereto. That is, the LDMOS transistor has to be operated under the voltage applied to the gate electrode 106 so as not to breakdown the gate oxide layer 104.
When the gate oxide layer 104 is formed with a thickness of 25 nm, for example, a voltage of 25 V or larger is known to cause the layer breakdown with relative ease, thereby indicating the voltage normally applied to the gate electrode 106 in the order of 15 V at most. As a result, the range of the gate voltage has to be set different from that of the drain voltage for driving the LDMOS transistors.
This is exemplified by DC/DC device products, in which the efficiency is one of the factors of practical importance for the products. In order to achieve the efficiency, inverter outputs are necessitated at the input potential (source voltage) and the ground potential.
Although one of the means for achieving the efficiency is to control the voltage input to the gate electrode, which is carried out by lowering this voltage by an internal stepdown circuit, for example, this method is not so efficient after all, since the efficiency is reduced to a certain degree since the steps of lowering the voltage are already involved. It is desirable, therefore, to obviate such a difficulty mentioned above.
There is a method previously known for preventing such difficulty, in which a bipolar transistor is utilized as a switching element having high withstand voltages in place of the LDMOS transistor.
Since the function of the base diffusion layer of bipolar transistor corresponds to that of the gate electrode of LDMOS transistor, the bipolar transistor is operated to control the input not by applied voltage, but by forward current flow. As a result, the input voltage is known as small as on the order of one volt.
In order to achieve low on resistance values for a bipolar transistor, the vertical type thereof is generally formed. In the vertically constructed bipolar transistor, however, the structure includes an epitaxial layer as the collector, a buried layer, and a collector wall diffusion layer for decreasing collector resistance. In addition, the structure has to also include an isolation diffusion layer for implement the diffusion isolation from other elements. The vertical bipolar transistor, therefore, has a drawback such as complicated process steps for the fabrication.
In contrast, another type of bipolar transistor is known with laterally constructed structure (lateral bipolar transistor), which can be fabricated with relatively simpler process steps.
In the lateral bipolar transistor, however, its collector-emitter distance has to be sufficiently separated to satisfy high withstand voltage requirements. Therefore, a difficulty arises in the lateral bipolar transistor, in that current amplification remains low compared with the vertical bipolar transistor, since the base width increases and the surface portion only between collector and gate is available for the current flow.
Thus, the present inventors have investigated in detail an LDMOS structure of the bipolar transistor, which can be fabricated with simpler process including the step of forming double diffusion structure with the layers of different conductivity types, which is carried out in the self-aligned manner with respect to a polysilicon gate electrode.
This LDMOS structure includes a drain diffusion layer, a channel diffusion layer, and a source diffusion layer. These layers are constructed to have a lateral bipolar structure in the region directly below a gate oxide layer, and a vertical bipolar transistor structure further below.
Therefore, when the drain, channel, and source diffusion layers are operated to function as a collector, base, and emitter, respectively, the bipolar transistor with the LDMOS structure may be capable of retaining high withstand voltages even after decreasing its base width.
However, there remains a difficulty yet to be solved for the LDMOS structure of the bipolar transistor, in that the gate oxide layer is deteriorated when high voltages are applied to the gate electrode.